Component selection is all about making hard decisions when determining what parts best suit your system needs. Common trade-offs include price vs. performance and integration vs. time-to-market. System-on-a-chip is a concept that is often discussed, written about and dreamed about. However, the realities of system design reveal flaws in the theoretical search for greater integration. To the first order, from a performance standpoint, integration is usually best. However, from a density and time-to-market standpoint, a discrete solution is often the better choice. A perfect example that illustrates these concepts can be found in the area of true dual-ported memory.
This article explores the trade-offs between integration and discrete solutions, looking specifically at dual-port SRAM integration. Flexibility and performance characteristics favor an integrated solution. Time-to-market, system simulation, process incompatibility and die size/density comparisons favor a discrete memory solution.
First and foremost, the integrated solution offers increased flexibility and the ability to utilize distributed memory. Within the ASIC, if an 8k x 24 dual-port memory is needed next to an integrated processor and two 1k x 100 dual-port memories are needed to buffer data at each serializer/deserializer (Serdes), then these exact configurations could be used. One would not need to revert to using a 512-kbit discrete dual-port memory, which is a higher number of bits than the ASIC design needs.
The ASIC part is also faster. Why? The answer lies in how cycle time is calculated. For a discrete solution, the tCD2 (clock to data valid) is added to the tSA (set-up time of the next chip) and the approximate time associated with the trace length to the next chip. This data is documented in figure 1, along with the resulting fMAX of 149 MHz. For an integrated solution, these values will drop considerably. Each component of cycle time is affected due to the extra package parasitics and inductance associated with driving signals on and off the chip. Several nanoseconds can be lost per device to the pc-board interface. That delay hampers the performance of discrete solutions.
So if the integrated solution is faster, has a higher bandwidth, and is more configurable, then why use a discrete solution? If the necessary dual-port cell is not readily available, then time-to-market is impacted. The time to get a new memory cell from specification to tapeout is approximately six to nine months (using 10 ASIC designers) for a pure digital ASIC. If a pure digital design is not possible, a mixed-signal design will take even longer due to the block design complexities. The expected 7.5 man-years is a significant resource expenditure when a discrete solution can be bought off the shelf.
Yet another problem arises with the integration itself, which is affected by process interoperability and simulation techniques. At the forefront are the limitations imposed by core voltages. Discrete component designers typically add voltage regulators to increase the voltages as needed. For instance, a 4-Mbit dual-port memory that is designed on a 0.18-micron process has a core voltage of 1.8 V. To create a 3.3-V part, designers add a voltage regulator to support the dual-port macro. An end system architect will then design a board with this discrete solution. Six months later, an ASIC designer will be charged with reducing system cost for volume production. The ASIC may also be on 0.18-micron TSMC process with 1.8-V voltage. Unfortunately, as an IP block, the dual-port is 3.3 V, regardless of what the unregulated voltage may be. This makes integration much more challenging and potentially impossible.
Once integrated, the ASIC lives and dies by timing analysis and system-level simulation (no transistor-level simulation). This creates a challenge, since the system simulation assumes that all blocks and cells have been properly characterized. Every gate must have a defined output-to-output timing. If the ASIC is not properly characterized, then the design may need to be redone if it does not meet spec. A specialty memory (dual-port) designer uses specialized full custom tools to extract the critical path for analog simulation using HSpice or Time Mill tools.
Since the ASIC designer extracts RCs from full chip to simulate, the simulation is not modular and is unable to look at the timing within the SRAM block. This creates an all or nothing proposition for that particular block of circuitry. Either the simulation works or it doesn't, much like the ASIC itself. This makes debugging virtually impossible. If the design is made up of discrete chips and separate interconnected models, then partial simulation is possible and debugging is more straightforward.
Assuming that process interoperability and simulation have been overcome, the most significant hurdles of all are die size and trying to reach the high density of dual-port memory needed by communications systems. A 4-Mbit true dual-port SRAM die size is between 100 and 120 mils2 using a 0.18-micron process. In order to bring this down to a number that is easily comparable to dual-port SRAM within an ASIC, it is necessary to subtract the voltage regulator and scribe (excess area used for testing that will be cut away when forming a packaged part). This number is then further broken into memory cell and logic. These blocks can then be compared to similar building blocks used in ASICs.
Memory processes are by nature more-suited to memory cell design. However, most ASIC processes are optimized for logic. The result is that although the memory cell portion of a discrete dual-port is roughly 50 percent smaller than the equivalent ASIC technology memory cell, once the logic is added back in, the discrete dual-port die size increases to about 75 percent the size of the ASIC die size. Figure 2 documents the resulting die size per Mbit of dual-ported memory for both discrete and integrated dual-ported memories. Obviously, this die size falls with process migration to smaller line widths.
This relative die size can then be translated into the ability to do higher density dual-ports both discretely and in an ASIC, which is captured by the lines moving up and to the right in figure 2. The end result: While the discrete 4.5-Mbit dual-port occupies a die size of about 120 mm2, the same portion of an ASIC die could accommodate only about 2.5 Mbits of density in a similar technology.
Despite this number, it is important to remember that the 120-mm2 dual-port die size is about the largest that it is practical to manufacture in a discrete device. Directly integrating that much dual-ported memory economically into an ASIC would be extremely difficult. When a communications system designer buys an off-the-shelf dual-port, the IC manufacturer has to deal with yield and fall-out, which, depending upon process defect density, begins as low as 50 percent from virgin wafer to finished part. By integrating the dual-port, the dual-port die size will lower the yield of the ASIC. If the dual-port portion of the ASIC has a 75 percent yield and the rest of the ASIC has a 75 percent yield, the overall ASIC yield is just over 50 percent, which is unacceptable. Taking this into account, a more realistically integrated dual-port memory would be on the order of 1 Mbit.
The question remains: To integrate or use discrete specialty memory? Provided the density needs are small and the designer needs more than 150 MHz, then it may be best to integrate. This particularly holds true if the memory needs are very diverse, small and distributed throughout the ASIC. However, as density needs increase to greater than 1 Mbit, the ability to integrate diminishes; at more than 2.5 Mbits, it is always better to purchase a discrete dual-port SRAM.
In the end, for those systems pushing the envelope in density, the right choice will continue to be discrete memories.
---
James Dillon is dual-port SRAM product manager and David Lindley is new product design program manager at Cypress Semiconductor (San Jose, Calif.). Dillon holds a BS in electrical engineering from the U.S. Military Academy. Lindley holds a BS in computer engineering from Mississippi State University.
http://www.isdmag.com
© 2002 CMP Media LLC.
1/1/02, Issue # 14151
